Quant & research
Reproducible and auditable AI inference evidence.
Deterministic computation, reproducible outputs, cryptographic receipts, audit trails, efficient numerical execution, and advanced transformer research - for people who need methods, not slogans.
LuxiEdge's deterministic numeric workload has also undergone independent TestFort evaluation, including H100 throughput, sustained API load, and CPU/GPU hash-matching tests.
Core capabilities
Faithful Llama 3.1 resident inference
Internal Llama 3.1 resident-inference milestone. Active-batch output matched the serial BF16 path on tested correctness gates. Independent validation of performance and energy is the next step.
Correctness gates passed internally; independent reproduction is on the validation roadmap. (Internal benchmark, not an MLPerf submission.)
TRADE residual stacks
Device-resident GPU stacks for multi-layer residual compute. Public 7B-class path: 28 layers × h=3584 on H100 NVL with multi-run throughput and sustain-only J/token.
AUDIT & receipts
Where the product lane demands it: cryptographic receipts, free-ride residual checks, and null-space behavior under load - not just marketing “determinism.”
WNSM free-ride
Null-space payload bus under real CUDA load. Public pack: free-ride vs side-channel H2D, null residual ~1e-8 class, single-layer null-inject drift 0 in the stack test path.
Long-context O(N) memory
Waller streaming state scales ~O(N) in memory vs dense scores ~O(N²). Public ladder through 32k (and analytical 131k memory reduction).
Convert + serve path
HF → Luxi native convert for 7B-class weights; serve and TRADE examples for operator evaluation. Implementation lives in the engineering repo; proof is public on LuxiDemo.
Deterministic math demo
Standalone binary: JSON expressions in, results + SHA256 out. Useful for integration smoke tests - secondary to the inference-energy thesis on this site.
Where we win, and where we are still measuring
| Axis | Status | Public proof |
|---|---|---|
| Faithful CUDA correctness | Full 28-layer Qwen2-7B on H100; CPU/CUDA and HF/CUDA greedy-token match rate 1.0 under the current acceptance protocol | Correctness results → |
| Internal prefill evidence (absolute and matched, separate) | Internal absolute prefill: ~44,860 positions per second at ~0.01532 board J/position (Qwen2-7B-class, seq 128, batch 72, dual-GEMM, no vLLM arm). Internal matched comparison: ~1.18x the tested vLLM at ~12% lower board J/position at batch 16, throughput variation below 1% across runs. Internal, prefill-stage evidence, each reported separately and separately from the independent TESTfort baseline; independent reproduction is the next step. | Internal prefill evidence → |
| Independent prefill baseline (TESTfort, 2026-07-23) | Independently verified 3.10% lower board J/position vs default vLLM at 80.60% of default vLLM throughput. TESTfort third-party measured, with the validation report published. Preserved as dated independent evidence with the complete tradeoff published. | Independent baseline → |
| Internal TRADE research (vs Hugging Face FP16) | Internal TRADE research path versus the stated Hugging Face Transformers FP16 reference - separate protocol, not a production-peer comparison. Measured numbers are kept in the research archive on Proof. | TRADE benchmark → |
| Earlier 7B-class TRADE sustain ladder @ seq≥128 | Separate public protocol | h100-7b-class-TRADE |
| Short-sequence throughput vs Flash | Complete head-to-head published, both sides | h100-stack12-H2H |
| Free-ride / AUDIT under load | Differentiated thesis | h100-WNSM-free-ride |
| Long-ctx memory scaling | O(N) vs O(N²) | h100-LONGCTX-scaling |